Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) full_time NEW

SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Full chip and block level timing signoff and convergence through timing ecos on post routed database for various timing signoff checks
• Full chip and block level front-end implementation from timing constraints development, synthesis, formal verification, power intent generation & validation
• Develop block and full chip level timing constraints for test modes
• Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
• Analysis of clock domain crossing paths at block and full chip level
• Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL
• Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis timing validation flows
• Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification
• Implement Functional ECOs for complex blocks
• Deploy and enhance methodology and flows related to timing constraint generation and verification and timing closure
• Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and route
• Work with multi-disciplinary groups to make sure RTL/Netlists are on schedule and delivered with the highest quality by incorporating automated checks at every stage of the design process

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of experience working as a synthesis and/or front-end STA engineer

PREFERRED SKILLS AND EXPERIENCE:

• Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in advanced nodes
• Experience with test modes, mode merging to optimize physical design implementation and STA Signoff.
• Experience with power intent and upf development for block and soc top.
• Familiar with formal verification and implementing functional ecos.
• Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations (AOCV, POCV based STA), voltage drop aware STA, and clock reconvergence pessimism removal
• Hands-on experience in industry standard physical synthesis and STA tools (Synopsys DC, Primetime or equivalent)
• Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure
• Deep understanding of ASIC design flow, top-down and bottom-up design methodologies
• Knowledge of low-power methodologies and leakage/dynamic power optimization flows and techniques
• Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
• Experience with high reliability design and implementations
• Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment  

ADDITIONAL REQUIREMENTS:

• Must be willing to travel when needed (typically <10%)
• Willing to work extended hours and weekends to meet critical deadlines, as needed

COMPENSATION & BENEFITS:    

Pay range:    
Synthesis and Front-End STA Engineer/Senior: $170,000.00 – $230,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.